Resistive random access memories (RRAM) have recently gained tremendous popularity due to fast (˜ns) resistance switching while consuming low power (<mW). A key advantage of RRAM is the scalability of its simple structure. However, at ˜10 nm design rules, the line resistance becomes too significant to ignore. Three dimensional (3D) non-volatile memories have been proposed to increase bit density at looser design rules, but each array layer stacked vertically adds area to the silicon periphery outside of the array, as well as many more additional film deposition and etching process steps, leading to a net increase in cost.